Non-interlocked system buses are characterized as having a data request cycle and a data return cycle which may be temporally separated. That is, an element which is connected to the system bus, or bus connection, may request access to data stored in another bus connection, for example, a system memory. This request cycle defines one bus transaction. Thereafter, the data is returned to the requester during another bus transaction. During the interval of time between the request and return transactions other bus connections may also make requests of the memory; these subsequent requests being queued by a memory controller and executed in sequence.
In order to identify the requester and the type of access required it is known to provide a group of signal lines on the system bus which define a unique identification (ID) associated with the requester and also the particular type of access, or command. In addition, another group of signal lines convey an address which identifies the source or sink location of the data while another group of signal lines is dedicated to the bidirectional transfer of the data itself.
As can be appreciated, the provision of discrete signal lines to convey the ID and command information necessitates the provision of associated signal paths and circuit elements connected to the signal paths. Such signal paths and circuit elements occupy some finite amount of volume and consume system power. In modern computer systems a desirable goal is the reduction of overall volume and power consumption and the dedication of available volume and power to highly integrated, and hence highly functional, components.
Furthermore, for those systems which employ one or more high speed cache memories tightly coupled to associated CPUs address information flowing over the system bus is typically monitored to determine if the associated data is contained within the cache memory and, if so, whether the cache is required to interrupt or otherwise intercede in a bus transaction in order to ensure that data accessed reflects the current state of that data.
During a write type of bus access, wherein the address and data information are simultaneously provided on the bus, it can be appreciated that the cache must very quickly decode and compare the address to those addresses presently stored within the cache in order to determine whether bus intervention is required. Inasmuch as a typical bus transaction may occur in a duration of time measured in some hundreds of nanoseconds, the necessary speed requirements of the cache are substantial.